? semiconductor components industries, llc, 2000 october, 2000 rev. 2 1 publication order number: mc100lvel37/d mc100lvel37 3.3vecl 1:4 1/ 2 clock fanout buffer the mc100lvel37 is a fully differential 1:4 fanout buffer. the device offers two outputs at 1 of the input frequency, and two outputs at 2 of the input frequency. the low outputoutput skew of the device makes it ideal for distributing 1x and 1/2x frequency synchronous signals. the differential inputs have special circuitry which ensures device stability under open input conditions. when both differential inputs are left open the clkn input will pull down to v ee , the clkn input will bias around v cc /2 and the qn output will go low. ? 700 ps typical propagation delays ? 50 ps maximum outputoutput skews ? esd protection: >2 kv hbm, >200 v mm ? the 100 series contains temperature compensation ? pecl mode operating range: v cc = 3.0 v to 3.8 v with v ee = 0 v ? necl mode operating range: v cc = 0 v with v ee = 3.0 v to 3.8 v ? internal input pulldown resistors ? qn output will default low with inputs open or at v ee ? meets or exceeds jedec spec eia/jesd78 ic latchup test ? moisture sensitivity level 1 for additional information, see application note and8003/d ? flammability rating: ul94 code v0 @ 1/8o, oxygen index 28 to 34 ? transistor count = 256 devices http://onsemi.com marking diagram* 1 20 a = assembly location wl = wafer lot yy = year ww = work week so20 dw suffix case 751d 100lvel37 awlyyww 1 20 device package shipping ordering information mc100lvel37dw so20 38 units/rail mc100lvel37dwr2 so20 1000 units/reel *for additional information, see application note and8002/d
mc100lvel37 http://onsemi.com 2 20lead pinout (top view) q0 q0 q1 q1 q2 q2 q3 q3 v cc clk0 clk0 clk_sel clk1 clk1 mr v ee 19 20 18 17 16 15 14 2 1 34567 v ee 13 8 12 9 11 10 v cc v cc v ee 1 2 warning: all v cc and v ee pins must be externally connected to power supply to guarantee proper operation. pin description function ecl differential clock 1 outputs ecl differential clock 2 outputs ecl differential clock inputs ecl input clock selection ecl asynchronous master reset positive supply negative supply pin q0, q0 ; q1, q1 q2, q2 ; q3, q3 clkn, clkn clk_sel mr v cc v ee truth table mr l l h clk_sel l h x q0, 1 clk0/ 1 clk1/ 1 l x = don't care q2, 3 clk0/ 2 clk1/ 2 l maximum ratings (note 1.) symbol parameter condition 1 condition 2 rating units v cc pecl mode power supply v ee = 0 v 8 to 0 v v ee necl mode power supply v cc = 0 v 8 to 0 v v i pecl mode input voltage v ee = 0 v v i v cc 6 to 0 v i c ode u o age necl mode input voltage ee 0 v cc = 0 v i cc v i v ee 6o0 6 to 0 v i out output current continuous surge 50 100 ma ma ta operating temperature range 40 to +85 c t stg storage temperature range 65 to +150 c q ja thermal resistance (junction to ambient) 0 lfpm 500 lfpm 20 soic 20 soic 140 100 c/w c/w q jc thermal resistance (junction to case) std bd 20 soic 30 to 35 c/w t sol wave solder <2 to 3 sec @ 248 c 265 c 1. maximum ratings are those values beyond which device damage may occur.
mc100lvel37 http://onsemi.com 3 lvpecl dc characteristics v cc = 3.3 v; v ee = 0.0 v (note 1) 40 c 25 c 85 c symbol characteristic min typ max min typ max min typ max unit i ee power supply current 38 50 38 55 38 55 ma v oh output high voltage (note 2.) 2215 2295 2420 2275 2345 2420 2275 2345 2420 mv v ol output low voltage (note 2.) 1470 1605 1745 1490 1595 1680 1490 1595 1680 mv v ih input high voltage (single ended) 2135 2420 2135 2420 2135 2420 mv v il input low voltage (single ended) 1490 1825 1490 1825 1490 1825 mv v ihcmr input high voltage common mode range (differential) (note 3.) vpp < 500 mv vpp 500 mv 1.3 1.5 2.9 2.9 1.2 1.4 2.9 2.9 1.2 1.4 2.9 2.9 v v i ih input high current 150 150 150 m a i il input low current clkn clkn 0.5 300 0.5 300 0.5 300 m a m a note: devices are designed to meet the dc specifications shown in the above table, after thermal equilibrium has been establishe d. the circuit is in a test socket or mounted on a printed circuit board and transverse air flow greater than 500 lfpm is maintained. 1. input and output parameters vary 1:1 with v cc . v ee can vary 0.3 v. 2. outputs are terminated through a 50 ohm resistor to v cc 2 volts. 3. v ihcmr min varies 1:1 with v ee , max varies 1:1 with v cc . the v ihcmr range is referenced to the most positive side of the differential input signal. normal operation is obtained if the high level falls within the specified range and the peak-to-peak voltage lies between v pp min and 1 v. lvnecl dc characteristics v cc = 0.0 v; v ee = 3.3 v (note 1.) 40 c 25 c 85 c symbol characteristic min typ max min typ max min typ max unit i ee power supply current 38 50 38 55 38 55 ma v oh output high voltage (note 2.) 1085 1005 880 1025 955 880 1025 955 880 mv v ol output low voltage (note 2.) 1830 1695 1555 1810 1705 1620 1810 1705 1620 mv v ih input high voltage (single ended) 1165 880 1165 880 1165 880 mv v il input low voltage (single ended) 1810 1475 1810 1475 1810 1475 mv v ihcmr input high voltage common mode range (differential) (note 3.) vpp < 500 mv vpp 500 mv 2.0 1.8 0.4 0.4 2.1 1.9 0.4 0.4 2.1 1.9 0.4 0.4 v v i ih input high current 150 150 150 m a i il input low current clkn clkn 0.5 300 0.5 300 0.5 300 m a m a note: devices are designed to meet the dc specifications shown in the above table, after thermal equilibrium has been establishe d. the circuit is in a test socket or mounted on a printed circuit board and transverse air flow greater than 500 lfpm is maintained. 1. input and output parameters vary 1:1 with v cc . v ee can vary 0.3 v. 2. outputs are terminated through a 50 ohm resistor to v cc 2 volts. 3. v ihcmr min varies 1:1 with v ee , max varies 1:1 with v cc . the v ihcmr range is referenced to the most positive side of the differential input signal. normal operation is obtained if the high level falls within the specified range and the peak-to-peak voltage lies between v pp min and 1 v.
mc100lvel37 http://onsemi.com 4 ac characteristics v cc = 3.3 v; v ee = 0.0 v or v cc = 0.0 v; v ee = 3.3 v (note 1.) 40 c 25 c 85 c symbol characteristic min typ max min typ max min typ max unit f max maximum toggle frequency tbd tbd tbd ghz t plh t phl propagation delay clk to q/q (diff) clk to q/q mr to q 640 620 640 940 920 920 680 680 680 700 700 700 920 940 920 720 720 720 980 970 980 ps t skew within-device skew (note 2.) duty cycle skew (diff) (note 3.) 50 50 50 50 50 50 ps t jitter cycletocycle jitter tbd tbd tbd ps v pp input swing (note 4.) 150 1000 150 1000 150 1000 mv t r t f output rise/fall times q (20% 80%) 280 550 280 550 280 550 ps 1. v ee can vary 0.3 v. 2. within-device skew defined as identical transitions on similar paths through a device. 3. duty cycle skew is the difference between a tplh and tphl propagation delay through a device. 4. v pp (min) is minimum input swing for which ac parameters guaranteed. the device has a dc gain of 40. v tt = v cc 2.0 v figure 1. typical termination for output driver and device evaluation (see application note and8020 termination of ecl logic devices.) driver device receiver device q qb d db 50 50 v tt resource reference of application notes an1404 eclinps circuit performance at nonstandard v ih levels an1405 ecl clock distribution techniques an1406 designing with pecl (ecl at +5.0 v) an1503 eclinps i/o spice modeling kit an1504 metastability and the eclinps family an1560 low voltage eclinps spice modeling kit an1568 interfacing between lvds and ecl an1596 eclinps lite translator elt family spice i/o model kit an1650 using wireor ties in eclinps designs an1672 the ecl translator guide and8001 odd number counters design and8002 marking and date codes and8020 termination of ecl logic devices
mc100lvel37 http://onsemi.com 5 package dimensions so20 dw suffix plastic soic package case 751d05 issue f 20 1 11 10 b 20x h 10x c l 18x a1 a seating plane h x 45 e d m 0.25 m b m 0.25 s a s b t e t b a dim min max millimeters a 2.35 2.65 a1 0.10 0.25 b 0.35 0.49 c 0.23 0.32 d 12.65 12.95 e 7.40 7.60 e 1.27 bsc h 10.05 10.55 h 0.25 0.75 l 0.50 0.90 0 7 notes: 1. dimensions are in millimeters. 2. interpret dimensions and tolerances per asme y14.5m, 1994. 3. dimensions d and e do not include mold protrusion. 4. maximum mold protrusion 0.15 per side. 5. dimension b does not include dambar protrusion. allowable protrusion shall be 0.13 total in excess of b dimension at maximum material condition.
mc100lvel37 http://onsemi.com 6 notes
mc100lvel37 http://onsemi.com 7 notes
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